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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad9873 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2000 analog front end converter for set-top box, cable modem functional block diagram dac inv sinc 12 tx interpolator filter pll dds sin cos 3 12 12 4 2 mux 8 8 10 12 tx iq tx sync serial itf profile rx sync rx iq rx if ad9873 ca sdelta0 sdelta1 ref clk i in q in if10 if12 video tx control functions rx adc adc adc adc features low-cost 3.3 v cmos analog front end converter for mcns-docsis, dvb, davic-compliant set-top box, cable modem applications 232 mhz quadrature digital upconverter dc to 65 mhz output bandwidth 12-bit direct if d/a converter (txdac+ ? ) programmable reference clock multiplier (pll) direct digital synthesis interpolator sin(x)/x compensation filter four programmable, pin-selectable modulator profiles single-tone mode for fr equency synthesis applications 12-bit, 33 msps sampling direct if a/d converter with auxiliary automatic clamp video input multiplexer 10-bit, 33 msps sampling direct if a/d converter dual 8-bit, 16.5 msps sampling iq a/d converter two independently programmable sigma-delta converters direct interface to ad8321/ad8323 pga cable driver programmable frequency output power-down modes applications cable and satellite systems pc multimedia digital communications data and video modems cable modem set-top boxes powerline modem broadband wireless communication general description the ad9873 integrates a complete 232 mhz quadrature digital transmitter and a multichannel receiver with four high- performance analog-to-digital converters (adc) for various video and digital data signals. the ad9873 is designed for cable modem set-top box applications, where cost, size, power dissi- pation, and dynamic performance are critical attributes. a single external crystal is used to control all internal conversion and data processing cycles. the transmit section of the ad9873 includes a high-speed direct digital synth esizer (dds), a high-performance, high-speed 12-bit digital-to-analog converter (dac), programmable clock multiplier circuitry, digital filters, and other digital signal processing functions, to form a complete quadrature digital up-converter device. on the receiver side, two 8-bit adcs are optimized for iq demodulated ?ut-of band?signals. an on-chip 10-bit adc is typically used as a direct if input of 256 qam modulated signals in cable modem applications. a second direct if input and an auxiliary video input with automatic programmable clamp function are multiplexed to a high-performance 12-bit video adc. the chip? programmable sigma-delta modulated outputs and an output clock may be used to control external components such as programmable gain amplifiers (pga) and mixer stages. three pins provide a direct interface to the ad8321/ad8323 programmable gain amplifier (pga) cable driver. the ad9873 is available in a spac e-saving 10 0-lead mqfp package. txdac+ is a registered trademark of analog devices, inc.
rev. 0 ad9873 C2C page features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . . . . 1 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 absolute maximum ratings . . . . . . . . . . . . . . . . 7 thermal characteristics . . . . . . . . . . . . . . . . . . 7 explanation of test levels . . . . . . . . . . . . . . . . 7 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 definitions of terms . . . . . . . . . . . . . . . . . . . . . . . 8 pin function descriptions . . . . . . . . . . . . . . . . . 9 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . 10 register bit definitions . . . . . . . . . . . . . . . . . . . 12 typical performance characteristics . . . 14 typical power consumption characteristics . . . . . . . . . 14 dual sideband transmit spectrum . . . . . . . . . . . . . . . . 14 single sideband transmit spectrum . . . . . . . . . . . . . . . 15 typical qam transmit performance characteristics . . 16 typical adc performance characteristics . . . . . . . . . . . 18 theory of operation . . . . . . . . . . . . . . . . . . . . . . 20 transmit section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 osc in clock multiplier . . . . . . . . . . . . . . . . . . . . . . . . 21 receive section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 clock and oscillator circuitry . . . . . . . . . . 22 programmable clock output ref clk . . . . 23 sigma-delta outputs . . . . . . . . . . . . . . . . . . . . . . 23 serial interface for register control . . . 23 general operation of the serial interface . . . . . . . . . . . . 23 instruction byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 serial interface port pin description . . . . . . . . . . . . . . . 24 msb/lsb transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 notes on serial port operation . . . . . . . . . . . . . . . . . . . 24 page transmit path (tx) . . . . . . . . . . . . . . . . . . . . . . . . . 24 transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 data assembler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 half-band filters (hbfs) . . . . . . . . . . . . . . . . . . . . . . . 25 cascaded integrator?omb (cic) filter . . . . . . . . . . 25 combined filter response . . . . . . . . . . . . . . . . . . . . . . . 25 inverse sinc filter (isf) . . . . . . . . . . . . . . . . . . . . . . . 27 tx signal level considerations . . . . . . . . . . . . . . . . . . . 28 tx throughput and latency . . . . . . . . . . . . . . . . . . . . . 28 d/a converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 programming/writing the ad8321/ad8323 cable driver amplifier gain control . . . 29 receive path (rx) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 adc theory of operation . . . . . . . . . . . . . . . . . . . . . . . 30 receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 driving the analog inputs . . . . . . . . . . . . . . . . . . . . . . . 30 op amp selection guide . . . . . . . . . . . . . . . . . . . . . . . . 31 adc differential inputs . . . . . . . . . . . . . . . . . . . . . . . . 31 adc voltage references . . . . . . . . . . . . . . . . . . . . . . . . 31 video input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 power and grounding considerations . . . 32 evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . 33 hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . 39 table of contents
rev. 0 C3C ad9873 (v as = 3.3 v 5%, v ds = 3.3 v 10%, f oscin = 27 mhz, f sysclk = 216 mhz, f mclk = 54 mhz (m = 8, n = 4), adc sample rate derived from pll f mclk , r set = 10 k , 75 dac load) test parameter temp level min typ max unit system clock, dac sampling f sysclk frequency range full iii 232 mhz osc in and xtal characteristics frequency range full iii 3 33 mhz duty cycle 25 c iii 35 50 65 % input capacitance 25 civ 3 pf input resistance 25 c iv 100 m ? mclk out jitter (f mclk derived from pll) 25 c iv 6 ps rms txdac characteristics 1 resolution n/a n/a 12 bits full-scale output current full iii 2 4 20 ma gain error (using internal reference) 25 c i ? 0.14 +3 % fs output offset 25 c i ? +1 % fs reference voltage (refio level) 25 c i 1.18 1.23 1.28 v differential nonlinearity (dnl) 25 civ 2.5 lsb integral nonlinearity (inl) 25 civ 8 lsb output capacitance 25 civ 5 pf phase noise @ 1 khz offset, 42 mhz 25 c iv ?13 dbc/hz output voltage compliance range full iii ?.5 +1.5 v wideband sfdr 5 mhz analog out, i out = 4 ma 25 c iv 59 dbc 65 mhz analog out, i out = 4 ma 25 c iv 54 dbc narrowband sfdr ( 100 khz window) 65 mhz analog out, i out = 4 ma 25 c iv 79 dbc tx modulator characteristics i/q offset full iii 50 55 db pass band amplitude ripple (f < f iqclk /8) full iii 0.1 db pass band amplitude ripple (f < f iqclk /4) full iii 0.5 db stop band response (f > f iqclk 3/4) full iii ?3 db 8-bit adc characteristics resolution n/a n/a 8 bits conversion rate full iii 16.5 mhz pipeline delay n/a n/a 3.5 adc cycles dc accuracy differential nonlinearity 25 civ 0.5 lsb integral nonlinearity 25 civ 0.5 lsb offset error for each 8-bit adc 25 civ 0.75 % fsr gain error for each 8-bit adc 25 civ 4 % fsr offset matching between 8-bit adcs full iv 3 lsb gain matching between 8-bit adcs full iv 4.5 lsb analog input input voltage range full iv 1 v p-p input capacitance 25 c iv 1.4 pf differential input resistance 25 civ 4 k ? aperture delay 25 c iv 2.0 ns aperture uncertainty (jitter) 25 c iv 1.2 ps rms input bandwidth (? db) 25 c iv 90 mhz input referred noise 25 c iv 600 v reference voltage error reft8?efb8 (0.5 v) 25 ci 4 92 mv dynamic performance (a in = ?.5 db fs, f = 5 mhz) signal-to-noise and distortion ratio (sinad) full ii 43.5 48 db specifications
rev. 0 C4C ad9873?pecifications test parameter temp level min typ max unit 8-bit adc characteristics (continued) dynamic performance (a in = ?.5 db fs, f = 5 mhz) effective number of bits (enob) full ii 6.9 7.68 bits effective number of bits (enob) 2 full iv 7.68 bits signal-to-noise ratio (snr) full ii 43.5 48 db total harmonic distortion (thd) full ii ?6 ?7 db spurious free dynamic range (sfdr) full ii 58 64 db differential phase 25 c iv <0.1 degree differential gain 25 c iv 1 lsb 10-bit adc characteristics resolution n/a n/a 10 bits conversion rate full iii 33 mhz pipeline delay n/a n/a 5.5 adc cycles dc accuracy differential nonlinearity 25 civ 0.75 lsb integral nonlinearity 25 civ 0.5 lsb offset error 25 civ 0.5 % fsr gain error 25 civ 3 % fsr analog input input voltage range full iv 2 v p-p input capacitance 25 c iv 1.4 pf differential input resistance 25 civ 4 k ? aperture delay 25 c iv 2.0 ns aperture uncertainty (jitter) 25 c iv 1.2 ps rms input bandwidth (? db) 25 c iv 95 mhz input referred noise 25 c iv 350 v reference voltage reft10?efb10 (1 v) 25 ci 6 200 mv dynamic performance (a in = ?.5 db fs, f = 5 mhz) signal-to-noise and distortion ratio (sinad) full ii 57.9 60.1 db effective number of bits (enob) full ii 9.3 9.7 bits effective number of bits (enob) 3 full iv 9.8 bits signal-to-noise ratio (snr) full ii 58.2 60.1 db total harmonic distortion (thd) full ii ?5.8 ?3.9 db spurious free dynamic range (sfdr) full ii 65.7 80 db differential phase 25 c iv <0.1 degree differential gain 25 c iv <1 lsb 12-bit adc characteristics resolution n/a n/a 12 bits conversion rate full iii 33 mhz pipeline delay n/a n/a 5.5 adc cycles dc accuracy differential nonlinearity 25 civ 0.75 lsb integral nonlinearity 25 civ 1.5 lsb offset error 25 civ 1 % fsr gain error 25 civ 2 % fsr analog input input voltage range full iv 2 v p-p input capacitance 25 c iv 1.4 pf differential input resistance 25 civ 4 k ? aperture delay 25 c iv 2.0 ns aperture uncertainty (jitter) 25 c iv 1.2 ps rms input bandwidth (? db) 25 c iv 85 mhz input referred noise 25 civ 75 v reference voltage reft12?efb12 (1 v) 25 ci 6 200 mv
rev. 0 C5C ad9873 test parameter temp level min typ max unit 12-bit adc characteristics (continued) dynamic performance (a in = ?.5 db fs, f = 5 mhz) signal-to-noise and distortion ratio (sinad) full iii 62.3 65 db signal-to-noise and distortion ratio (sinad) 3 full iv 67.4 db effective number of bits (enob) full iii 10.0 10.5 bits effective number of bits (enob) 3 full iv 10.8 bits signal-to-noise ratio (snr) full iii 63.3 65.3 db signal-to-noise ratio (snr) 3 full iv 67.4 db total harmonic distortion (thd) full iii ?7.6 ?5.4 db total harmonic distortion (thd) 3 full iv ?7.6 db spurious free dynamic range (sfdr) full iii 65.7 80 db spurious free dynamic range (sfdr) 3 full iv 80 db differential phase 25 c iv <0.1 degree differential gain 25 c iv <1 lsb video clamp input input voltage range full iv 2 v clamp current positive 25 c iv 1.3 ma clamp droop current 25 civ 2 a clamp level offset programming range 25 c iii 256 512 2032 lsb clamp level resolution 25 c iv 16 lsb carrier rejection filter bandwidth (? db) 25 c iv 0.6 mhz dynamic performance (a in = ?.5 db fs, f = 5 mhz) signal-to-noise and distortion ratio (sinad) full iv 52 db effective number of bits (enob) full iv 8.34 bits signal-to-noise ratio (snr) full iv 61.0 db total harmonic distortion (thd) full iv ?3.0 db spurious free dynamic range (sfdr) full iv 55.0 db differential phase 25 c iv <0.1 degree differential gain 25 c iv <8 lsb channel-to-channel isolation tx dac-to-adc isolation (5 mhz analog output) isolation between tx and 8-bit adcs 25 c iv >80 db isolation between tx and 10-bit adc 25 c iv >85 db isolation between tx and 12-bit adc 25 c iv >90 db adc-to-adc isolation (a in = ?.5 db fs, f = 5 mhz) isolation between if12 and video 25 c iii 70 >70 db isolation between if10 and if12 25 c iv >80 db isolation between q in and if10 25 c iv >80 db isolation between q in and i inputs 25 c iv >70 db timing characteristics (20 pf load) wake-up time n/a n/a 200 t mclk cycles minimum reset pulsewidth low (t rl ) n/a n/a 5 t mclk cycles digital output rise/fall time 25 c iii 2.8 4 ns tx/rx interface mclk frequency (f mclk )25 c iii 66 mhz txsync/txiq set up time (t su )25 c iii 3 ns txsync/txiq hold time (t hd )25 c iii 3 ns rxsync/rxiq/if to valid time (t tv )25 c iii 5.2 ns rxsync/rxiq/if hold time (t ht )25 c iii 0.2 ns serial control bus sclk frequency (f sclk ) full iii 15 mhz clock pulsewidth high (t pwh ) full iii 30 ns clock pulsewidth low (t pwl ) full iii 30 ns clock rise/fall time full iii 1 ms data/chip-select setup time (t ds ) full iii 25 ns data hold time (t dh ) full iii 0 ns data valid time (t dv ) full iii 30 ns
rev. 0 C6C ad9873?pecifications test parameter temp level min typ max unit cmos logic inputs logic ??voltage 25 c iii 2.0 v logic ??voltage 25 c iii 0.8 v logic ??current 25 c iii 12 a logic ??current 25 c iii 12 a input capacitance 25 civ 3 pf cmos logic outputs (1 ma load) logic ??voltage 25 c iii 2.4 v logic ??voltage 25 c iii 0.4 v power supply analog supply current i as 25 c ii 91 115 ma digital supply current i ds full operating conditions 4 (register 02h = 00h) 25 c iv 250 ma zero input tx 4 (register 02h = 00h) 25 c ii 175 205 ma 25% tx burst duty cycle 4 (register 02h = 00h) 25 c iv 210 ma power-down digital tx (register 02h = 20h) 25 cii 42 55 ma power supply rejection (differential signal) tx dac 25 c iv <0.25 % fs 8-bit adc 25 c iv <0.004 % fs 10-bit adc 25 c iv <0.002 % fs 12-bit adc 25 c iv <0.0004 % fs notes 1 single tone generated by applying a 1.6875 mhz sine signal to the q channel and the 90 degree phase shifted (cosine) signal to t he i channel. 2 sampling directly with f osccin /2. no degradation due to clock multiplier pll. adc clock select register 08h, bits 5 and 7 set to ?. 3 sampling directly with f osccin . no degradation due to clock multiplier pll. adc clock select register 08h, bits 5 and 7 set to ?. 4 see performance graph tpc 2 for power saving in burst mode operation.
rev. 0 ad9873 C7C absolute maximum ratings * power supply (vas, vds) . . . . . . . . . . . . . . . . . . . . . . 3.9 v digital output current . . . . . . . . . . . . . . . . . . . . . . . . . 5 ma digital inputs . . . . . . . . . . . . . . . ?.3 v to drvdd + 0.3 v analog inputs . . . . . . . . . . . . . ?.3 v to avdd (iq) +0.3 v operating temperature . . . . . . . . . . . . . . . . . . . . 0 c to 70 c maximum junction temperature . . . . . . . . . . . . . . . . 150 c storage temperature . . . . . . . . . . . . . . . . . . ?5 c to +150 c lead temperature (soldering 10 sec) . . . . . . . . . . . . . 300 c * absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. functional operability under any of these conditions is not necessarily implied. exposure of absolute maximum rating conditions for extended periods of time may affect device reliability. explanation of test levels i 100% production tested. ii devices are 100% production tested at 25 c and guaran- teed by design and characterization testing for commer cial operating temperature range (0 c to 70 c). iii parameter is guaranteed by design and/or characteriz- ation testing. iv parameter is a typical value only. n/a test level definition is not applicable. thermal characteristics thermal resistance 100-lead mqfp ja = 40.5 c/w caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9873 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device ordering guide temperature package package model range description option ad9873js 0 c to 70 c metric quad flatpack (mqfp) s-100c AD9873-EB evaluation board
rev. 0 ad9873 C8C definitions of terms differential nonlinearity error (dnl, no missing codes) an ideal converter exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. guaranteed no missing codes to 10-bit resolution indicates that all 1024 codes respectively, must be present over all operating ranges. integral nonlinearity error (inl) linearity error refers to the deviation of each individual code from a line drawn from ?egative full scale?through ?ositive full scale.?the point used as ?egative full scale?occurs 1/2 lsb before the first code transition. ?ositive full scale?is defined as a level 1 1/2 lsb beyond the last code transition. the deviation is measured from the middle of each particular code to the true straight line. phase noise single-sideband phase noise power density is s pecified relative to the carrier (dbc/hz) at a given frequency offset (1 khz) from the carrier. phase noise can be measured direc tly in single tone transmit mode with a spectrum analyzer that supports noise marker measurements. it detects the relative power between the carrier and the offset (1 khz) sideband noise and takes the reso- lution bandwidth (rbw) into account by subtracting 10 log (rbw). it also adds a correction factor that compensates for the imple- mentation of the resolution bandwidth, log display and detector characteristic. output compliance range the range of allowable voltage at the output of a current-output dac. operation beyond the maximum compliance limits may cause either output stage saturation, resulting in nonlinear per- formance or breakdown. spurious-free dynamic range (sfdr) the difference, in db, between the rms amplitude of the dacs output signal (or adc? input signal) and the peak spurious signal over the specified bandwidth (nyquist bandwidth unless otherwise noted). pipeline delay (latency) the number of clock cycles between conversion initiation and the associated output data being made available. offset error first transition should occur for an analog value 1/2 lsb above negative full scale. offset error is defined as the deviation of the actual transition from that point. gain error the first code transition should occur at an analog value 1/2 lsb above negative full scale. the last transition should occur for an analog value 1 1/2 lsb below the nominal full scale. gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. aperture delay aperture delay is a measure of the sample-and-hold amplifier (sha) performance and specifies the time delay between the rising edge of the sampling clock input to when the input signal is held for conversion. aperture uncertainty (jitter) aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the adc. signal-to-noise + distortion (sinad) ratio sinad is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for sinad is expressed in decibels. effective number of bits (enob) for a sine wave, sinad can be expressed in terms of the number of bits. using the following formula, n = ( sinad ?1.76) db/6.02 it is possible to obtain a measure of performance expressed as n , the effective number of bits. signal-to-noise ratio (snr) snr is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. total harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmonic com- ponents to the rms value of the measured input signal and is expressed as a percentage or in decibels. power supply rejection power supply rejection specifies the converters maximum full- scale change when the supplies are varied from nominal to minimum and maximum specified voltages. channel-to-channel isolation (crosstalk) in an ideal multichannel system, the signal in one channel will not influence the signal level of another channel. the channel- to-channel isolation specification is a measure of the change that occurs to a grounded channel as a full-scale signal is applied to another channel.
rev. 0 ad9873 C9C pin function descriptions pin no. mnemonic pin function 1, 84, 87 avdd analog supply voltage 92, 95 10-/12-bit adc 2, 21, 70 drgnd pin driver digital ground 3, 22, 72 drvdd pin driver digital supply voltage 4?5 if11?f0 multiplexed output of if10- and if12-bit adcs 16?9 rx iq 3 multiplexed output of i and ?x iq 0 q 8-bit adcs 20 rx sync demultiplexer synchronization output for if and iq adcs 23 mclk master clock output demultiplexer 24, 33, 38 dvdd digital supply voltage 25, 34, dgnd digital ground 39, 40 26 tx sync synchronization input for transmitter 27?2 tx iq 5 multiplexed i and q input tx iq 0 data for transmitter (two? complement) 35, 36 profile[1:0] profile selection inputs 37 reset master reset input, reset ap plies for all interfaces and registers 41 sclk serial interface input clock 42 cs serial interface chip select 43 sdio serial interface data i/o 44 sdo serial interface data output 45 dgnd tx digital ground tx section 46 dvdd tx digital supply voltage tx 47 pwr down transmit power-down control input 48 refio dac bandgap requires 0.1 f capacitor to ground 49 fsadj full-scale dac current output adjust with external resistor 50 agnd tx analog ground tx section 51 tx transmitter dac output 52 tx+ transmitter dac output+ 53 avdd tx analog supply voltage tx 54 dgnd pll pll digital ground 55 dvdd pll pll digital supply voltage 56 avdd pll pll analog supply voltage 57 pll filter pll loop filter connection 58 agnd pll pll analog ground 59 dgnd osc digital ground oscillator 60 xtal crystal oscillator inv. output 61 osc in oscillator clock input 62 dvdd osc digital supply oscillator 63 ca clk cable amplifier control clock output pin no. mnemonic pin function 64 ca data cable amplifier control data output 65 ca enable cable amplifier control enable output 66 dvdd sd supply voltage sigma delta 67 sdelta1 sigma delta output stream 1 68 sdelta0 sigma delta output stream 0 69 dgnd sd ground sigma delta 71 ref clk programmable reference clock output derived from mclk 73 avdd iq analog supply 8-bit adcs 74, 77, 80 agnd iq analog ground 8-bit adcs 75 refb8 bottom reference decoupling iq 8-bit adc? reference 76 reft8 top reference decoupling iq 8-bit adc? reference 78 i in inverting i analog input 79 i in+ noninverting i analog input 81 q in inverting q analog input 82 q in+ noninverting q analog input 83, 88, 91, agnd analog ground 10-/12-bit adc 96, 99 85 refb10 bottom reference decoupling if 10-bit adc? reference 86 reft10 top reference decoupling if 10-bit adc? reference 89 if10 noninverting if10 analog input 90 if10+ inverting if10 analog input 93 refb12 bottom reference decoupling if 12-bit adc? reference 94 reft12 top reference decoupling if 12-bit adc? reference 97 if12 inverting if12 analog input 98 if12+ noninverting if12 analog input 100 video in single-ended video input
rev. 0 ad9873 C10C pin configuration 5 4 3 2 7 6 9 8 1 11 10 16 15 14 13 18 17 20 19 22 21 12 24 23 26 25 28 27 30 29 32 33 34 35 36 38 39 40 41 42 43 44 45 46 47 48 49 50 31 37 76 77 78 79 74 75 72 73 70 71 80 65 66 67 68 63 64 61 62 59 60 69 57 58 55 56 53 54 51 52 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 pin 1 identifier top view (pins down) video in agnd if12+ if12 agnd avdd reft12 refb12 avdd agnd if10+ if10 agnd avdd reft10 refb10 avdd agnd q in+ q in txiq(1) txiq(0) dvdd dgnd profile(1) profile(0) reset dvdd dgnd dgnd sclk cs sdio sdo dgnd tx dvdd tx pwr down refio fsadj agnd tx agnd iq i in+ i in agnd iq reft8 refb8 agnd iq avdd iq drvdd ref clk drgnd dgnd sd sdelta 0 sdelta 1 dvdd sd ca enable ca data ca clk dvdd osc osc in xtal dgnd osc agnd pll pll filter avdd pll dvdd pll dgnd pll avdd tx tx+ tx drgnd drvdd (msb) if(11) if(10) if(9) if(8) if(7) if(6) if(5) if(4) if(3) if(2) if(1) if(0) ( msb) rxiq(3) rxiq(2) rxiq(1) rxiq(0) rxsync drgnd drvdd mlck dvdd dgnd txsync (msb) txiq(5) txiq(4) txiq(3) txiq(2) ad9873 avdd
rev. 0 ad9873 C11C table i. register map address default (hex) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (hex) type 00 sdio lsb/msb reset osc in osc in osc in osc in osc in 10 rw bidirectional first multiplier multiplier multiplier multiplier multiplier m <4> m <3> m <2> m <1> m <0> 01 pll osc in mclk mclk mclk mclk mclk mclk 09 rw lock divider divider divider divider divider divider divider detect n = 3 (4) r <5> r <4> r <3> r <2> r <1> r <0> 02 power-down power-down power-down power-down power-down power-down power-down power-down 00 rw pll dac tx digital tx 12-bit adc reference 10-bit adc reference 8-bit adc 12-bit adc 10-bit adc 03 sigma-delta output 0 control word <3:0> lsb 000000rw 04 sigma-delta output 0 control word <11:4> msb 00 rw 05 sigma-delta output 1 control word <3:0> lsb 000000rw 06 sigma-delta output 1 control word <11:4> msb 00 rw 07 video input clamp level control for video input <6:0> 20 rw adc enable 08 adc clock 0 adc clock 0 0 0 test test 00 rw adc select select 12-bit adc 10-bit adc 090 0 0 0000000rw 0a0 0 0 0000000rw 0b0 0 0 0000000rw 0c 0 0 0 0 version <3:0> 0x r 0d0 0 0 0000000r 0e0 0 0 0000000r 0f 0 0 profile profile 0 bypass spectral single-tone 00 rw tx select <1> select <0> inv. sinc inversion tx tx mode tx filter 10 tx frequency turning word profile 0 <7:0> 00 rw tx 11 tx frequency turning word profile 0 <15:8> 00 rw tx 12 tx frequency turning word profile 0 <23:16> 00 rw tx 13 cable driver amplifier gain control profile 0 <7:0> 00 rw tx 14 tx frequency turning word profile 1 <7:0> 00 rw tx 15 tx frequency turning word profile 1 <15:8> 00 rw tx 16 tx frequency turning word profile 1 <23:16> 00 rw tx 17 cable driver amplifier gain control profile 1 <7:0> 00 rw tx 18 tx frequency turning word profile 2 <7:0> 00 rw tx 19 tx frequency turning word profile 2 <15:8> 00 rw tx 1a tx frequency turning word profile 2 <23:16> 00 rw tx 1b cable driver amplifier gain control profile 2 <7:0> 00 rw tx 1c tx frequency turning word profile 3 <7:0> 00 rw tx 1d tx frequency turning word profile 3 <15:8> 00 rw tx 1e tx frequency turning word profile 3 <23:16> 00 rw tx 1f cable driver amplifier gain control profile 3 <7:0> 00 rw tx ??register bits should not be programmed with 1.
rev. 0 ad9873 C12C register bit definitions 00h, bits 0?: osc in multiplier?egister address this register field is used to program the on-chip multiplier (pll) that generates the chip? high-frequency system clock, f sysclk . for example, to multiply the external crystal clock f oscin by 19 decimal, program register address 00h, bits 5? as 13h. default value is m = 16 = 10h. valid entries range from m = 1 to 31. m = 1 (no pll) requires a very stable, high-frequency clock at osc in. a changed f sysclk frequency is stable (pll locked) after a maximum of 200 f mclk cycles (= wake-up time). 00h, bit 5: reset writing a one to this bit resets the registers to their default val- ues and restarts the chip. the reset bit always reads back 0. register address 00h bits are not cleared by this software reset. however, a low level at the reset pin would force all registers, including all bits in address 00h, to their default state. 00h, bit 6: lsb/msb first active high indicates spi serial port access of instruction byte and data registers is least significant bit (lsb) first. default low indicates most significant bit (msb) first format. 00h, bit 7: sdio bidirectional default low indicates spi serial port uses dedicated input/output lines (sdio and sdo pin). high configures serial port as single line i/o (sdio pin is used bidirectional). 01h, bits 0?: mclk divider this register is used to divide the chip? master clock by r, w here r is an integer between 2 and 63. the generated refer ence clock, ref clk, can be used for external frequency-controlled devices. default value is r = 9. 01h, bit 6: osc in divider the osc in multiplier output clock can be divided by 4 or 3 to generate the chip? master clock. active high indicates a divide ratio of n = 3. default low configures a divide ratio of n = 4. 01h, bit 7: pll lock detect if this bit is set to 1, ref clk pin is disabled from the nor- mal usage. in this mode ref clk high signals that the internal phase lock loop (pll) is in lock with clk in. 02h bits 0?: power-down sections of the chip that are not used can be put in a power saving mode when the corresponding bits are set to 1. this register has a default value of 00h with all sections active. bit 0: power-down 8-bit adc powers down the 8-bit adc and stops rxsync framing signal. bit 1: power-down 10-bit adc reference powers down the internal 10-bit adc reference. bit 2: power-down 10-bit adc powers down the 10-bit adc. bit 3: power-down 12-bit adc reference powers down the internal 12-bit adc reference. bit 4: power-down 12-bit adc powers down the 12-bit adc. bit 5: power-down tx powers down the transmit section of the chip. bit 6: power-down dac tx powers down the dac. bit 7: power-down pll powers down the clk in multiplier. 03h to 06h: sigma-delta output control words the sigma-delta output control words ? and ? are 12 bits wide and split in msb bits <11:4> and lsb bits <3:0>. c hanges to the sigma-delta outputs take effect immediately for every msb or lsb register write. sigma-delta output control words have a default value of 0. the smaller the programmed values in these registers, the lower are the integrated (low-pass filtered) sigma delta output levels (straight binary format). 07h, bits 0?: clamp level control for video input a 7-bit clamp level offset can be set for the internal automatic clamp level control loop of the video input. clamp level offset = clamp level control 16. this register defaults to 32 = 20h, which amounts to a clamp level offset of 512 lsb = 200h. valid clamp level control values are 16 to 127. 07h, bit 7: video input enable this bit controls the multiplexer to the 12-bit adc and deter- mines if if12 input or video input is used. the bit is default set to 0 for the if12 input. 08h, bit 0: test 10-bit adc active high allows nonmultiplexed 10-bit adc data only to be read at if outputs. output data changes at half mclk clock rate. this bit defaults to 0. 08h, bit 1: test 12-bit adc active high allows nonmultiplexed 12-bit adc data only to be read at if outputs. output data changes at half mclk clock rate. this bit defaults to 0. 08h, bit 5 and bit 7: adc clock select active high indicates that the frequency at osc in is directly used to sample the on chip adcs. default low indicates that the on chip adcs generate their sampling frequencies from the intern ally generated master clock mclk. both bit 5 and bit 7 need to be programmed with the same values. 0ch, bits 0?: version this register stores the die version of the chip. it can only be read. 0fh, bit 0: single-tone tx mode active high configures the ad9873 for single-tone applications. the ad9873 will supply a single frequency output as determined by the frequency tuning word (ftw) selected by the active profile. in this mode, the tx iq input data pins are ignored but should be tied high or low. default value of sin gle-tone tx mode is 0 (inactive). 0fh, bit 1: spectral inversion tx when set to 1, inverted modulation is performed (i cos ( t ) + q sin ( t )). default is logic zero, noninverted modulation (i cos ( t ) ?q sin ( t )). 0fh, bit 2: bypass inv sinc tx filter active high, configures the ad9873 to bypass the sin(x)/x compensation filter. default value is 0 (inverse sinc filter en abled).
rev. 0 ad9873 C13C 0fh, bit 4, bit 5: profile select the ad9873 quadrature digital upconverter is capable of storing four preconfigured modulation modes called profiles that define a transmit frequency tuning word and cable driver amplifier con- trol. profile select bits <1:0> or profile [1:0] pins program the current register profile to be used. profile select bits should always be 0 if profile pins are used to switch between pro- files. using the profile select bits as a means of switching between different profiles requires the profile pins to be tied low. 10h?fh: burst parameter tx frequency tuning words the frequency tuning word (ftw) determines the dds- generated carrier frequency (f c ) and is formed via a concatenation of register addresses. bit 7 of register address 1ah is the most significant bit of the profile 2-frequency tuning word. bit 0 of register address 18h is the least significant bit of the profile 2-frequency tuning word. the output frequency equation is given as: f c = ( ftw f sysclk )/2 24 . where f sysclk = mx f oscin and ftw < 80 00 00 h changes to ftw bytes immediately take effect on active profiles. cable driver gain control the ad9873 dedicates three output pins that directly inter face to the ad832x-family of gain programmable cable driver am plifier. this allows direct control of the cable driver? gain via the ad9873. new data is automatically sent to the cable driver ampli fier whenever a new burst profile with different gain setting becomes active or when the gain contents of an active ad8321/ ad8323 gain control register changes. default value is 00h (lowest gain).
rev. 0 ad9873 C14C typical performance characteristics (v as = 3.3 v, v ds = 3.3 v, f oscin = 27 mhz, f sysclk = 216 mhz, f mclk = 54 mhz [m = 8, n = 4], adc sample rate derived directly from f oscin , r set = 10 k [i out = 4 ma], 75 dac load, unless otherwise noted) f sysclk mhz 380 240 120 140 supply current ma 180 220 340 320 280 200 260 240 220 300 360 160 200 tpc 1. power consumption vs. clock speed, f sysclk duty cycle % 340 300 030 supply current ma 70 90 320 310 100 290 50 80 20 40 60 single-tone 16-qam 330 10 tpc 2. power consumption vs. transmit burst duty cycle typical power consumption characteristics (20 mhz single tone, unless otherwise noted) frequency mhz 0 60 06 magnitude db 14 18 20 100 40 20 80 10 16 4812 10 30 50 2 90 70 tpc 3a. dual sideband spectral plot, f c = 5 mhz f = 1 mhz, r set =10 k ? (i out = 4 ma), rbw = 1 khz frequency mhz 0 60 55 61 magnitude db 69 73 20 100 40 75 80 65 71 59 63 67 10 30 50 57 90 70 tpc 4a. dual sideband spectral plot, f c = 65 mhz f = 1 mhz, r set =10 k ? (i out = 4 ma), rbw = 1 khz dual sideband transmit spectrum (see table iv for dual-tone generation.) frequency mhz 0 60 06 magnitude db 14 18 20 100 40 20 80 10 16 4812 10 30 50 2 90 70 tpc 3b. dual sideband spectral plot, f c = 5 mhz f = 1 mhz, r set = 4 k ? (i out = 10 ma), rbw = 1 khz frequency mhz 0 60 55 61 magnitude db 69 73 20 100 40 75 80 65 71 59 63 67 10 30 50 57 90 70 tpc 4b. dual sideband spectral plot, f c = 65 mhz f = 1 mhz, r set = 4 k ? (i out = 10 ma), rbw = 1 khz
rev. 0 ad9873 C15C frequency mhz 0 60 0 magnitude db 80 20 100 40 80 40 20 60 10 30 50 90 70 100 tpc 5a. single sideband @ 65 mhz, rbw = 2 khz f c = 66 mhz, f = 1 mhz, r set = 10 k ? (i out = 4 ma) frequency mhz 0 60 0 magnitude db 80 20 100 40 80 40 20 60 10 30 50 90 70 100 tpc 6a. single sideband @ 42 mhz, rbw = 2 khz f c = 43 mhz, f = 1 mhz, r set = 10 k ? (i out = 4 ma) frequency mhz 0 60 0 magnitude db 80 20 100 40 80 40 20 60 10 30 50 90 70 100 tpc 7a. single sideband @ 5 mhz, rbw = 2 khz f c = 6 mhz, f = 1 mhz, r set = 10 k ? (i out = 4 ma) frequency mhz 0 60 0 magnitude db 80 20 100 40 80 40 20 60 10 30 50 90 70 100 -./& 11>'&785=6#08 / 6''786,78 1- 6%0 ? (i out = 10 ma) frequency mhz 0 60 0 magnitude db 80 20 100 40 80 40 20 60 10 30 50 90 70 100 -./' 11>%#785=6#08 / 6%$786,78 1- 6%0 ? (i out = 10 ma) frequency mhz 0 60 0 magnitude db 80 20 100 40 80 40 20 60 10 30 50 90 70 100 -./( 11>&785=6#08 / 6'786,78 1- 6%0 ? (i out = 10 ma) single sideband transmit spectrum
rev. 0 ad9873 C16C frequency offset mhz 0 60 2.5 1.0 magnitude db 1.0 2.0 20 90 40 2.5 80 0 1.5 1.5 0.5 0.5 10 30 50 2.0 70 tpc 8a. single sideband @ 65 mhz, rbw = 500 hz f c = 66 mhz, f = 1 mhz, r set = 10 k ? (i out = 4 ma) frequency offset khz 0 60 50 20 magnitude db 20 40 20 100 40 50 80 030 30 10 10 10 30 50 40 70 90 tpc 9. single sideband @ 65 mhz, rbw = 50 hz f c = 66 mhz, f = 1 mhz, r set = 10 k ? (i out = 4 ma) frequency mhz 0 60 0 magnitude db 35 20 80 40 15 525 10 30 50 70 45 40 20 10 30 50 tpc 11. 16-qam @ 42 mhz spectral plot, rbw = 1 khz frequency offset mhz 0 60 2.5 1.0 magnitude db 1.0 2.0 20 90 40 2.5 80 0 1.5 1.5 0.5 0.5 10 30 50 2.0 70 tpc 8b. single sideband @ 65 mhz, rbw = 500 hz f c = 66 mhz, f = 1 mhz, r set = 4 k ? (i out = 10 ma) frequency offset khz 0 60 2.5 1.0 magnitude db 1.0 2.0 20 100 40 2.5 80 0 1.5 1.5 0.5 0.5 10 30 50 2.0 70 90 tpc 10. single sideband @ 65 mhz, rbw = 10 hz f c = 66 mhz, f = 1 mhz, r set = 10 k ? (i out = 4 ma) frequency mhz 0 60 0 magnitude db 35 20 80 40 15 525 10 30 50 70 45 40 20 10 30 50 tpc 12. 16-qam @ 5 mhz spectral plot, rbw = 1 khz typical qam transmit performance characteristics (16-qam, 2.56 mbit/s sinc filter enabled, s quare root raised cosine filter with alpha = 0.25, r set = 4 k [i out = 10 ma], f sysclk = 163.84 mhz, f oscin = 20.48 mhz [m = 8, n = 4].)
rev. 0 ad9873 C17C tpc 13. tx output 16-qam analysis tpc 14. tx output 64-qam analysis
rev. 0 ad9873 C18C typical adc performance characteristics (adc sample rate derived directly from f oscin = 27 mhz [13.5 msps for 8-bit adcs], single-tone 5 mhz input signal, unless otherwise noted.) input signal frequency mhz 70 20 snr db 45 60 60 10 40 80 0 50 100 50 30 70 90 65 55 12-bit adc 10-bit adc 8-bit adc tpc 15. snr vs. input frequency input signal frequency mhz 70 20 sinad db 45 60 10 40 80 0 50 100 50 30 70 90 60 55 65 12-bit adc 10-bit adc 8-bit adc 11.34 7.18 8.01 9.67 8.84 10.51 enob bit tpc 16. sinad vs. input frequency input signal frequency mhz 65 6 magnitude db 40 14 410 18 220 12 816 55 50 60 snr 45 sfdr sinad tpc 17. video input characteristics vs. input frequency input signal frequency mhz 85 20 sfdr db 55 65 60 10 40 80 0 60 100 50 30 70 90 75 80 70 10-bit adc 8-bit adc 12-bit adc tpc 18. sfdr vs. input frequency input signal frequency mhz 60 20 thd db 80 60 10 40 80 0 74 100 50 30 70 90 64 66 62 12-bit adc 10-bit adc 8-bit adc 78 70 72 76 68 tpc 19. thd vs. input frequency frequency mhz 5 2 magnitude db 125 45 6 14 0 85 5 3 105 25 65 0 tpc 20. 8-bit adc single-tone spectral plot using pll (input frequency = 5 mhz, 2048 point fft)
rev. 0 ad9873 C19C frequency mhz 5 4 magnitude db 125 45 12 28 0 85 10 6 105 25 65 13.5 0 tpc 21. 12-bit adc single-tone spectral plot using pll (input frequency = 10 mhz, 4096 point fft) frequency mhz 5 4 magnitude db 125 45 12 28 0 85 10 6 105 25 65 13.5 0 tpc 22. 10-bit adc single-tone spectral plot using pll (input frequency = 10 mhz, 4096 point fft) frequency mhz 5 4 magnitude db 125 45 12 28 0 85 10 6 105 25 65 13.5 0 tpc 23. video input single-tone spectral plot using pll (input frequency = 5 mhz, 4096 point fft) frequency mhz 5 4 magnitude db 125 45 12 28 0 85 10 6 105 25 65 13.5 0 -./#% ,#?5 /1?- 1
. = .33 9 b
c6,78%+'. bb-< frequency mhz 5 4 magnitude db 125 45 12 28 0 85 10 6 105 25 65 13.5 0 tpc 25. 10-bit adc single-tone spectral plot without pll (input frequency = 10 mhz, 4096 point fft) frequency mhz 5 4 magnitude db 125 45 12 28 0 85 10 6 105 25 65 13.5 0 tpc 26. video input single-tone spectral plot without pll (input frequency = 5 mhz, 4096 point fft)
rev. 0 ad9873 C20C theory of operation to gain a general understanding of the ad9873 it is helpful to refer to figure 1, which displays a block diagram of the de vice mux 8 8 10 12 ad9873 i input q input if10 input if12 input video input adc adc adc adc dac 2 (f oscin ) 2 (f oscin ) 2 mux mux ref-8 ref-10 ref-12 clamp level 12 control word 0 12 control word 1 osc in multiplier m m = 1,2,.......,31 dac 12 mux inv sinc sin cos dds 12 12 12 12 12 12 2 2 r n 8 r = 2,3,.......,63 n = 3,4 (f mclk )(f iqclk ) i q 6 data assembler half-band filter #1 half-band filter #2 cic filter quadrature modulator ad832x ctrl burst profile ctrl serial interface 3 2 4 rx - itf sdelta1 sdelta0 osc in xtal tx fsadj tx iq tx sync mclk ref clk rx iq rx sync rx if inv sinc bypass (f oscin ) (f sysclk ) 4 12 - - figure 1. block diagram architecture. the following is a general description of the device functionality. later sections will detail each of the data path bu ild- ing blocks.
rev. 0 ad9873 C21C single-tone output transmit operation the ad9873 can be configured for frequency synthesis applica- tions by writing the single-tone bit true, and applying a clock signal (e.g., rx sync) to the tx sync pin. in single-tone mode, the ad9873 disengages the modulator and preceding data path logic to output a spectrally pure single frequency sine wave. the ad9873 provides for a 24-bit frequency tuning word, which results in a tuning resolution of 12.9 hz at a f sysclk rate of 216 mhz. a good rule of thumb when using the ad9873 as a frequency synthesizer is to limit the fundamental output frequ ency to 30% of f sysclk . this avoids generating aliases too close to the desired fundamental output frequency, thus minimizing the cost of filtering the aliases. all applicable programming features of the ad9873 apply when configured in single-tone mode. these features include: 1. frequency hopping via the profile inputs and associated tuning word, which allows frequency shift keying (fsk) modulation. 2. ability to bypass the sin(x)/x compensation filter. 3. power-down modes. osc in clock multiplier as mentioned earlier, the output data is sampled at the rate of f sysclk . since the ad9873 is designed to operate at f sysclk frequencies up to 232 mhz, there is the potential difficulty of trying to provide a stable input clock f oscin . although stable, high-frequency oscillators are available commercially, they tend to be cost prohibitive and create noise coupling issues on the printed circuit board. to alleviate this problem, the ad9873 has a built-in programmable clock multiplier and an oscillator circuit. this allows the use of a relatively low frequency (thus, less expensive) crystal or oscillator to generate the osc in signal. the low frequency osc in signal can then be multiplied in frequency by an integer factor of between 1 and 31, inclusive, to become the f sysclk clock. for dds applications, the carrier is typically limited to about 30% of f sysclk . for a 65 mhz carrier, the recommended system clock is above 216 mhz. the osc in multiplier function maintains clock integrity as evidenced by the ad9873? system phase noise characteris tics of ?13 dbc/hz. ex ternal loop filter components consis ting of a series resistor (1.3 k ? ) and capacitor (0.01 f) provide the compensation zero for the clk in multiplier pll loop. the overall loop per formance has been optimized for these compo- nent values. receive section the ad9873 includes four high-speed, high-performance adcs. two matched 8-bit adcs are optimized for analog iq demodu- lated signals and can be sampled with up to 16.5 msps. a direct if 10-bit adc and a 12-bit adc can digitize signals at a maxi- mum sampling frequency of 33 msps. input signal selection to the 12-bit adc can be programmed to either direct if or video (ntsc/pal). a programmable automatic clamp control pro- vides black level offset correction for video signals. the adc sampling frequency can either be derived directly from the osc in crystal or from the on-chip osc in multiplier. for highest dynamic performance it is recommended to choose a osc in frequency that can be used to directly sample the adcs. transmit section modulation mode operation the ad9873 accepts 6-bit words, which are strobed synchro nous to the master clock mclk into the data assembler. tx sync signals the start of a transmit symbol. two successive 6-bit w ords form a 12-bit symbol component. the incoming data is assumed to be complex, in that alternating 12-bit words are regarded as the inphase (i) and quadrature (q) components of a symbol. symbol components are assumed to be in two? complement format. the rate at which the 6-bit words are presented to the ad9873 will be referred to as the master clock rate (f mclk ). the data assembler splits the incoming data words into separate i/q data streams. the rate at which the i/q data word pairs appear at the output of the data assembler will be referred to as the i/q sample rate (f iqclk ). since two 6-bit input data words are used to con- struct each individual i and q data paths, it should be apparent that the input 6-bit data rate f mclk is four times the i/q sample rate (f mclk = 4 f iqclk ). once through the data assembler, the i/q data streams are fed through two half-band filters (half-band filters #1 and #2). the combination of these two filters results in a factor of four (4) increase of the sample rate. thus, at the output of half-band filter #2, the sample rate is 4 f iqclk . in addition to the sample rate increase, the half-band filters provide the low-pass filtering characteristic necessary to suppress the spectral images pro duced by the upsampling process. after passing through the half-band filter stages, the i/q data streams are fed to a cascaded integrator-comb (cic) filter. this filter is configured as an interpolating filter, which allows further upsampling rates of 3 or 4. the cic filter, like the half-bands, has a built-in low-pass characteristic. again, this provides for sup pres- sion of the spectral images produced by the upsampling process. the digital quadrature modulator stage following the cic filters is used to frequency-shift the baseband spectrum of the incom- ing data stream up to the desired carrier frequency (this process is known as upconversion ). the carrier frequency is numerically controlled by a direct d igital synthesizer (dds). the dds uses its internal reference clock (f sysclk ) to generate the desired carrier frequency with a high degree of precision. the carrier is applied to the i and q multi- pliers in quadrature fashion (90 phase offset) and summed to yield a data stream that is at the modulated carrier. it should be noted at this point that the incoming symbols have been converted from an input sample rate of f iqclk to an output sample rate of f sysclk (see figure 1). the modulated carrier is ultim ately destined to serve as the input to the digital-to-analog converter (dac) integrated on the ad9873. the dac output spectrum is distorted due to the intrinsic zero- order hold effect associated with dac-generated signals. this distortion is deterministic and follows the familiar sin(x)/x (or sinc) envelope. since the sinc distortion is predictable, it is also correctable. hence, the presence of the op tional inverse sinc filter preceding the dac. this is a fir filter, which has a transfer function conforming to the inverse of the sinc response. thus, when selected, it modifies the incoming data stream so that the sinc distortion, which would otherwise appear in the dac output spectrum, is virtually eliminated.
rev. 0 ad9873 C22C digital 8-bit adc outputs are multiplexed to one 4-bit bus, clocked by a frequency (f mclk ) of four times the sampling rate whereas the 10- and 12-bit adcs are multiplexed together to one 12-bit bus clocked by f mclk, which is two times their sampling frequency. clock and oscillator circuitry the ad9873? internal oscillator generates all sampling clocks from a simple, low-cost, series resonance, fundamental fre quency quartz crystal. figure 2 shows how the quartz crystal is con nected between osc in (pin 61) and xtal (pin 60) with parallel resonant load capacitors as specified by the crystal manufac turer. the internal oscillator circuitry can also be overdriven by a ttl level clock applied to osc in with xtal left unconnected. f osc in = f mclk n / m an internal phase locked loop (pll) generates the dac sam pling frequency f sysclk by multiplying osc in frequency m times (register address 00h). the mclk signal (pin 23) f mclk is derived by dividing this pll output frequency with the interpo- lation rate n of the cic filter stages (register address 01h). f sysclk = f osc in m f mclk = f osc in m / n an external pll loop filter (pin 57) con sisting of a series re sistor and ceramic capacitor (figure 15, r1 = 1.3 k ? , c12 = 0.01 f) is required for stability of the pll. also, a shield surrounding these components is recommended to minimize external noise cou pling into the pll? voltage controlled oscillator input (guard trace connected to avdd pll). figure 1 shows that adcs are either directly sampled by a low- jitter clock at osc in or by a clock that is derived from the pll output. operating modes can be selected in register address 08. sampling the adcs directly with the osc in clock requires mclk to be programmed to be twice the osc in frequency. 5 4 3 2 7 6 9 8 1 11 10 16 15 14 13 18 17 20 19 22 21 12 24 23 26 25 28 27 30 29 32 33 34 35 36 38 39 40 41 42 43 44 45 46 47 48 49 50 31 37 76 77 78 79 74 75 72 73 70 71 80 65 66 67 68 63 64 61 62 59 60 69 57 58 55 56 53 54 51 52 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 pin 1 identifier top view (pins down) video in agnd if12+ if12 agnd avdd reft12 refb12 avdd agnd if10+ if10 agnd avdd reft10 refb10 avdd agnd q in+ q in tx iq(1) tx iq(0) dvdd dgnd profile(1) profile(0) reset dvdd dgnd dgnd sclk cs sdio sdo dgnd tx dvdd tx pwrdown refio fsadj agnd tx agnd iq i in+ i in agnd iq reft8 refb8 agnd iq avdd iq drvdd ref clk drgnd dgnd so sdelta0 sdelta1 dvdd sd ca enable ca data ca clk dvdd osc os in xtal dgnd osc agnd pll pll filter avdd pll dvdd pll dgnd pll avdd tx tx+ tx drgnd drvdd (msb) if(11) if(10) if(9) if(8) if(7) if(6) if(5) if(4) if(3) if(2) if(1) if(0) (msb) rx iq(3) rx iq(2) rx iq(1) rx iq(0) rx sync drgnd drvdd mlck dvdd dgnd tx sync (msb) tx iq(5) tx iq(4) tx iq(3) tx iq(2) ad9873 avdd c7 0.1 f c8 0.1 f c9 0.1 f cp2 10 f c4 0.1 f c5 0.1 f c6 0.1 f cp1 10 f c1 0.1 f c2 0.1 f c3 0.1 f c10 20pf c11 20pf r1 1.3k cp3 10 f c12 0.01 f guard trace c13 0.1 f r set 10k figure 2. basic connections diagram
rev. 0 ad9873 C23C programmable clock output ref clk the ad9873 provides a frequency programmable clock output ref clk (pin 71). mclk (f mclk ) and the master clock di vider ratio r stored in register address 01h determine its frequency: f ref clk = f mclk / r sigma-delta outputs the ad9873 contains two independent sigma-delta outputs that when low-pass filtered generate level programmable dc voltages of: v sd = ( sigma - delta code )/4096)( v logic1 ) + v logic0 (influenced by cmos logic output levels.) 8 t mclk 000h 001h 002h 800h fffh 8 t mclk 4096 8 t mclk 4096 8 t mclk figure 3. sigma-delta output signals in cable modem set-top box applications the outputs can be used to control external variable gain amplifiers and rf tuners. a simple single-pole r-c low-pass filter provides sufficient filtering (see figure 4). 12 12 8 sigma-delta 1 sigma-delta 0 control word 1 control word 0 mclk r r c c dc (0.4 to drvdd-0.6v) dc (0.4 to drvdd-0.6v) typical: r = 50k c = 0.01 f f 3db = 1/(2 rc) = 318hz ad9873 figure 4. sigma-delta rc filter in more demanding applications where additional gain, level- shift or drive capability is required, a first or second order active filter might be considered for each sigma-delta output (see figure 5). sigma-delta r c v dc = (v sd /2 + v offsetref ) (1 + r/r1) gain = (1 + r/r1)/ 2 v offset = v offsetref (1 + r/r1) typical: r = 50k c = 0.01 f f 3db = 1/(2 rc) = 318hz ad9873 r v offsetref op250 r1 r c figure 5. sigma-delta active filter with gain and offset serial interface for register control the ad9873 serial port is a flexible, synchronous serial communi- cations port allowing easy interface to many industry standard microcontrollers and microprocessors. the serial i/o is com- patible with most synchronous transfer formats, including both the motorola spi and intel ssr protocols. the interface allows read/ write access to all registers that configure the ad9873. single or multiple byte transfers are supported as well as msb first or lsb first transfer formats. the ad9873? serial interface port can be configured as a single pin i/o (sdio) or two unidirectional pins for in/out (sdio/sdo). general operation of the serial interface there are two phases to a communication cycle with the ad9873. phase 1 is the instruction cycle, which is the writing of an in struc- tion byte into the ad9873, coincident with the first eight sclk rising edges. the instruction byte provides the ad9873 serial port controller with information regarding the data transfer cycle, w hich is phase 2 of the communication cycle. the phase 1 instruction byte defines whether the upcoming data transfer is read or write, the number of bytes in the data transfer and the starting register address for the first byte of the data transfer. the first eight sclk rising edges of each communication cycle are used to write the instruction byte into the ad9873. the remaining sclk edges are for phase 2 of the communica tion cycle. phase 2 is the actual data transfer between the ad9873 and the system controller. phase 2 of the communication cycle is a transfer of 1, 2, 3, or 4 data bytes as determined by the instruction byte. normally, using one multibyte transfer is the preferred method. however, single byte data transfers are useful to reduce cpu overhead when register access requires one byte only. registers change immediately upon writing to the last bit of each transfer byte. instruction byte the instruction byte contains the following information as shown in table ii: table ii. instruction byte information i7 i6 i5 i4 i3 i2 i1 i0 r/w n1 n0 a4 a3 a2 a1 a0 msb lsb r/w, bit 7 of the instruction byte, determines whether a read or a write data transfer will occur after the instruction byte write. logic high indicates read operation. logic zero indicates a write operation. n1, n0, bits 6 and 5 of the instruction byte, determine the number of bytes to be transferred during the data transfer cycle. the bit decodes are shown in the table iii. table iii. decode bits n1 n0 description 0 0 transfer 1 byte 0 1 transfer 2 bytes 1 0 transfer 3 bytes 1 1 transfer 4 bytes a4, a3, a2, a1, a0, bits 4, 3, 2, 1, 0, of the instruction byte, determine which register is accessed during the data transfer portion of the communications cycle. for multibyte transfers, this address is the starting byte address. the remaining register addresses are generated by the ad9873.
rev. 0 ad9873 C24C serial interface port pin description sclk?erial clock. the serial clock pin is used to synchronize data to and from the ad9873 and to run the internal state machines. sclk maximum frequency is 15 mhz. all data input to the ad9873 is registered on the rising edge of sclk. all data is driven out of the ad9873 on the falling edge of sclk. cs?hip select. active low input starts and gates a communi- cation cycle. it allows more than one device to be used on the same serial communications lines. the sdo and sdio pins will go to a high impedance state when this input is high. chip select sh ould stay low during the entire communication cycle. sdio?erial data i/o. data is always written into the ad9873 on this pin. however, this pin can be used as a bidirectional data line. the configuration of this pin is controlled by bit 7 of register address 0h. the default is logic zero, which configures the sdio pin as unidirectional. sdo?erial data out. data is read from this pin for protocols that use separate lines for transmitting and receiving data. in the case where the ad9873 operates in a single bidirectional i/o mode, this pin does not output data and is set to a high imped- ance state. msb/lsb transfers the ad9873 serial port can support both most significant bit (msb) first or least significant bit (lsb) first data formats. this functionality is controlled by register address, 0h, bit 6. the de fault is msb first. when this bit is set active high, the ad9873 serial port is in lsb first format. that is, if the ad9873 is in lsb first mode, the instruction byte must be written from least significant bit to most significant bit. multibyte data transfers in msb format can be completed by writing an instruction byte that includes the register address of the most significant byte. in msb first mode, the serial port internal byte address generator decrements for each byte required of the multibyte communication cycle. multibyte data transfers in lsb first format can be completed by writing an instruction byte that includes the register address of the least significant byte. in lsb first mode, the serial port internal byte address generator increments for each byte required of the multibyte communication cycle. the ad9873 serial port controller address will increment from 1fh to 00h for multibyte i/o operations if the msb first mode is active. the serial port controller address will decrement from 00h to 1fh for multibyte i/o operations if the lsb first mode is active. notes on serial port operation the ad9873 serial port configuration bits reside in bits 6 and 7 of register address 00h. it is important to note that the configu- ration changes immediately upon writing to the last bit of the register. for multibyte transfers, writing to this register may occur during the middle of a communication cycle. care m ust be taken to compensate for this new configuration for the remain- ing bytes of the current communication cycle. the same considerations apply to setting the reset bit in reg- ister address 00h. all other registers are set to their default values, but the software reset does not affect the bits in register address 00h. it is recommended to use only single byte transfers when chang- ing serial port configurations or initiating a software reset. a write to bits 1, 2, and 3 of address 00h with the same logic levels as for bits 7, 6, and 5 (bit pattern: xy1001yx binary), allows the user to reprogram a lost serial port configuration and to reset the regis ters to their default values. a second write to address 00h with reset bit low and serial port configuration as specified above (xy) reprograms the osc in multiplier setting. a changed f sysclk frequency is stable after a maximum of 200 f mclk cycles (= wake?p time). i6 (n) instruction cycle data transfer cycle cs sclk sdio sdo r/w i5 (n) i4 i3 i2 i1 i0 d7 n d6 n d2 0 d1 0 d0 0 d2 0 d1 0 d0 0 d7 n d6 n figure 6a. serial register interface timing msb-first instruction cycle data transfer cycle cs sclk sdio sdo i4 i3 i2 i1 i0 d7 n d6 n d2 0 d1 0 d0 0 i5 (n) i6 (n) r/w d2 0 d1 0 d0 0 d7 n d6 n figure 6b. serial register interface timing lsb-first cs sclk sdio t ds t sclk t pwl t dh t pwh instruction bit 7 instruction bit 6 t ds figure 7. timing diagram for register write to ad9873 data bit n data bit n 1 cs sclk sdio sdo t dv b
* -

+*($ transmit path (tx) transmit timing the ad9873 provides a master clock mclk and expects 6-bit multiplexed tx iq data on each rising edge. transmit symbols are framed with the tx sync input. tx sync high indicates the start of a transmit symbol. four consecutive 6-bit data packages form a symbol (i msb, i lsb, q msb, and q lsb). data assembler the input data stream is representative complex data. two 6-bit words form a 12-bit symbol component (two? complement format). four input samples are required to produce one i/q data pair. the i/q sample rate f iqclk at the input to the first half-band filter is a quarter of the input data rate f mclk .
rev. 0 ad9873 C25C txi[11:6] t hd t su mclk tx sync tx iq txi[5:0] txq[5:0] txq[11:6] txi[11:6]' txi[5:0]' txq[5:0]' txq[11:6]' txi[5:0]" txi[11:6]" figure 9. transmit timing diagram the i/q sample rate f iqclk puts a bandwidth limit on the maxi- mum transmit spectrum. this is the familiar nyquist limit and is equal to one-half f iqclk which hereafter will be referred to as f nyq . half-band filters (hbfs) hbf 1 is a 15-tap filter that provides a factor-of-two increase in sampling rate. hbf 2 is an 11-tap filter offering an additional factor-of-two increase in sampling rate. together, hbf 1 and 2 provide a factor-of-four increase in the sampling rate (4 f iqclk or 8 f nyq ). in relation to phase response, both hbfs are linear phase filters. as such, virtually no phase distortion is introduced within the passband of the filters. this is an important feature as phase distortion is generally intolerable in a data transmission system. cascaded integrator?omb (cic) filter a cic filter is unlike a typical fir filter in that it offers the flexibility to handle differing input and output sample rates (only in integer ratios, however). in the purest sense, a cic filter can provide either an increase or a decrease in sample rate at the output relative to the input, depending on the architecture. if the integration stage precedes the comb stage, the cic filter provides sample rate reduction (decimation). when the comb stage precedes the integrator stage, the cic filter provides an in crease in sample rate (interpolation). in the ad9873, the cic filter is configured as a programmable inter- polator and provides a sample rate increase by a factor of r = 3 or r = 4. in addition to the ability to provide a change in sample rate between input and output, a cic filter also has an intrinsic low-pass frequency response characteristic. the frequency response of a cic filter is dependent on three factors: 1. the rate change ratio, r. 2. the order of the filter, n. 3. the number of unit delays per stage, m. it can be shown that the system function h(z), of a cic filter is given by: hz r z zr z rm n k k rm n () = ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? 11 1 1 1 0 1 the form on the far right has the advantage of providing a result for z = 1 (corresponding to zero frequency or dc). the alternate form yields an indeterminate form (0/0) for z = 1, but is other- wise identical. the only variable parameter for the ad9873 s cic filter is r; m and n are fixed at 1 and 3, respectively. thus, the cic system function for the ad9873 simplifies to: hz r z zr z r k k r () = ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? 11 1 1 1 3 0 1 3 the transfer function is given by: hf r e er fr f jfr jf () sin( ) sin( ) () = ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? ? ? 11 1 1 2 2 3 3 the frequency response in this form is such that f is scaled to the output sample rate of the cic filter. that is, f = 1 corre sponds to the frequency of the output sample rate of the cic filter. h(f/r) will yield the frequency response with respect to the input sample of the cic filter. combined filter response the combined frequency response of hbf 1, hbf 2 and cic is shown in figure 10a to 10c and figure 11a to 11c. the usable bandwidth of the filter chain puts a limit on the m axi- mum data rate that can be propagated through the ad9873. a look at the passband detail of the combined filter response (figure 10d and figure 11d) indicates that in order to maintain an amplitude error of no more than 1 db, we are restricted to signals having a bandwidth of no more than about 60% of f nyq . thus, in order to keep the bandwidth of the data in the flat por tion of the filter passband, the user must oversample the baseband data by at least a factor of two prior to presenting it to the ad9873. note that without oversampling, the nyquist bandwidth of the baseband data corresponds to the f nyq . as such, the upper end of the data bandwidth will suffer 6 db or more of attenuation due to the frequency response of the digital filters. furtherm ore, if the baseband data applied to the ad9873 has been p ulse-shaped, there is an additional concern. typically, pulse-shaping is ap plied to the baseband data via a filter having a raised cosine response. in such cases, an value is used to modify the bandwidth of the data where the value of is such that 0 1. a value of 0 causes the data bandwidth to correspond to the nyquist bandwidth. a value of 1 causes the data bandwidth to be extended to twice the nyquist bandwidth. thus, with 2 oversampling of the baseband data and = 1, the nyquist bandwidth of the data will corre spond with the i/q nyquist bandwidth. as stated earlier, this results in problems near the upper edge of the data bandwidth due to the frequency response of the filters. the maximum value of that can be implemented is 0.45. this is because the data bandwidth becomes: 1/2(1+ ) f nyq = 0.725 f nyq , which puts the data bandwidth at the extreme edge of the flat portion of the filter response.
rev. 0 ad9873 C26C if a particular application requires an value between 0.45 and 1, the user must oversample the baseband data by at least a factor of four. the combined hb1, hb2, and cic filter introduces, over the frequency range of the data to be transmitted, a worst-case droop of less than 0.2 db. frequency fs/2 0 1.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10 0 magnitude db 10 20 30 40 50 60 70 80 figure 10a. cascaded filter 12 interpolator (n = 3) frequency fs/2 0 1.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10 0 magnitude db 10 20 30 40 50 60 70 80 figure 10b. input signal spectrum (n = 3), = 0.25 frequency fs/2 0 1.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10 0 magnitude db 10 20 30 40 50 60 70 80 figure 10c. response to input signal spectrum (n = 3) frequency fs/2 0 1.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10 0 magnitude db 10 20 30 40 50 60 70 80 figure 11a. cascaded filter 16 interpolator (n = 4) frequency fs/2 0 1.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10 0 magnitude db 10 20 30 40 50 60 70 80 figure 11b. input signal spectrum (n = 4), = 0.25 frequency fs/2 0 1.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10 0 magnitude db 10 20 30 40 50 60 70 80 figure 11c. response to input signal spectrum (n = 4)
rev. 0 ad9873 C27C frequency relative to i/q nyq. bw 0 1.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 magnitude db 1 2 3 4 5 6 figure 10d. cascaded filter passband detail (n = 3) frequency fs/2 0 1.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.35 magnitude db 1.36 1.37 1.38 1.39 1.40 1.41 1.42 1.43 1.44 1.45 figure 12b. sinc compensated response frequency fs/2 01.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.5 magnitude db 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 isf sinc figure 12a. sinc and isf filter response frequency relative to i/q nyq. bw 0 1.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 magnitude db 1 2 3 4 5 6 b
,, /b
. 9!6%< inverse sinc filter (isf) the ad9873 transmit section is almost entirely digital. the input signal is made up of a time series of digital data words. these data words propagate through the device as numbers. ultim ately, this number stream must be converted to an analog signal. to this end, the ad9873 incorporates an integrated dac. the output waveform of the dac is the familiar staircase pattern typical of a signal that is sampled and quantized. the staircase pattern is a result of the finite time that the dac holds a quantized level until the next sampling instant. this is known as a zero-order hold function. the spectrum of the zero-order hold function is the familiar sin(x)/x, or sinc, envelope. the series of digital data words presented at the input of the dac represent an impulse stream. it is the spectrum of this impulse stream, which is the characteristic of the desired output signal. due to the zero-order hold effect of the dac, however, the output spectrum is the product of the zero-order hold spectrum (the sinc envelope) and the fourier transform of the impulse stream. thus, there is an intrinsic distortion in the output spectrum, which follows the sinc response. the sinc response is deterministic and totally predictable. t hus, it is possible to predistort the input data stream in a manner, which compensates for the sinc envelope distortion. this can be accomplished by means of an isf. the isf incorporated on the ad9873 is a 5-tap, linear phase fir filter. its frequency response characteristic is the inverse of the sinc envelope and it equalizes the sinc droop up to 0.6 times the nyquist fre- quency. figure 12a and figure 12b show the effectiveness of the isf in correcting for the sinc distortion. figure 12a includes a graph of the sinc envelope and isf response while figure 12b shows the system response (which is the product of the sinc and isf responses). it should be mentioned at this point that the isf exhibits an insertion loss of 1.4 db. thus, signal levels at the output of the ad9873 with the isf bypassed are 1.4 db higher than with the isf engaged. however, for modulated output signals, which have a relatively wide bandwidth, the ben- efits of the sinc compensation usually outweighed the 1.4 db loss in output level. the decision of whether or not to use the isf is an application specific system design issue.
rev. 0 ad9873 C28C x q i z x figure 13. 16-quadrature modulation tx signal level considerations the quadrature modulator itself introduces a maximum gain of 3 db in signal level. to visualize this, assume that both the i data and q data are fixed at the maximum possible digital value, x. then the output of the modulator, z, is: z = [ x cos ( t ) x sin ( t )] it can be shown that z assumes a maximum value of zxxx =+ () = 22 2 (a gain of +3 db). however, if the same number of bits were used to represent the z values, as is used to represent the x values, an overflow w ould occur. to prevent this possibility, an effective 3 db attenuation is internally imple- mented on the i and q data path. zx =+ () = ? ? ? ? 12 12 // the following example assumes a pk/rms level of 10 db: maximum symbol component input value = (2047 lsbs 0.2 db ) = 2000 lsbs maximum complex input rms value = 2000 lsbs + 6 db pk/rms ( db ) = 1265 lsbs rms maximum complex input rms value calculation uses both i and q symbol components which adds a factor of 2 (= 6 db) to the formula. table iv. i? input test signals input level modulator output level single-tone (fc f) i = cos(f) fs 0.2 db fs 3.0 db q = cos(f + 90 ) = sin(f) fs 0.2 db single-tone (fc + f) i = cos(f) fs 0.2 db fs 3.0 db q = cos(f + 270 ) = sin(f) fs 0.2 db dual-tone (fc f) i = cos(f) fs 0.2 db fs q = cos(f + 180 ) = cos(f) or q = cos(f) fs 0.2 db if inv sinc filter is enabled, an insertion loss of ~1.4 db (for low frequencies) occurs at the dac output (see figure 12a, 12b). programming the ad9873 to single-tone transmit mode while disabling the inv sinc filter (address 0fh) generates a maximum (fs) amplitude single tone with a frequency (fc) determined by the associated frequency tuning word. table iv shows typical i q input test signals with amplitude levels related to 12-bit full scale (fs). tx throughput and latency data inputs effect the output fairly quickly but remain effective due to ad9873 s filter characteristics. data transmit latency through the ad9873 is easiest to describe in terms of f sysclk clock cycles (4 f mclk ). the numbers quoted are when an effect is first seen after an input value change. latency of i/q data entering the data assembler (ad9873 input) to the dac output is 119 f sysclk clock cycles (29.75 f mclk cycles). dc values applied to the data assembler input will take up to 176 f sysclk clock cycles (44 f mclk cycles) to propagate and settle at the dac output. enabling the inverse sinc filter adds only 2 f sysclk clock cycles latency. frequency hopping is accomplished via changing the profile input pins. the time required to switch from one frequency to another is less than 234 f sysclk cycles with the inverse sinc filter engaged. with the inverse sinc filter bypassed, the latency drops to less than 232 f sysclk cycles (58.5 f mclk cycles). d/a converter a 12-bit digital-to-analog converter (dac) is used to convert the digitally processed waveform into an analog signal. the w orst- case spurious signals due to the dac are the harmonics of the fundamental signal and their aliases. (please see the ad9851 data sheet for a detailed explanation of aliased images.) the w ideband 12-bit dac in the ad9873 maintains spurious-free dynamic range (sfdr) performance of 59 dbc up to f out = 42 mhz and 54 dbc up to f out = 65 mhz. the conversion process will produce aliased components of the fundamental signal at n f sysclk f carrier (n = 1, 2, 3). these are typically filtered with an external rlc filter at the dac output. it is important for dac inv sinc filter 0db 1.4db 12 hbf + cic interpolator +0.2db hbf + cic interpolator +0.2db attenuator 3db modulator 3db max i oo i 12 12 i o complex data input attenuator 3db two's complement format figure 14. signal level contribution
rev. 0 ad9873 C29C this analog filter to have a sufficiently flat gain and linear phase resp onse across the ban dwidth of interest to avoid modulation impairments. a relatively inexpensive fifth order elliptical low-pass filter is sufficient to suppress the aliased components for hfc network applications. the ad9873 provides true and complement current outputs. the full-scale output current is set by the rset resistor at pin 49. the value of rset for a particular iout is determined using the following equation: rset = 32 v dacrset / i out = ~ 39.4/ i out for example, if a full-scale output current of 20 ma is desired, then rset = (39.4/0.02) ? , or approximately 2 k ? . every dou- bling of the rset value will halve the output current. m aximum output current is specified as 20 ma. the full-scale output current range of the ad9873 is 2 ma to 20 ma. full-scale output currents outside of this range will degrade sfdr performance. sfdr is also slightly affected by output matching, that is, the two outputs should be terminated equally for best sfdr performance. the output load should be located as close as possible to the ad9873 package to minimize stray capacitance and inductance. the load may be a simple resistor to ground, an op amp current-to-voltage converter, or a transformer-coupled circuit. it is best not to attempt to directly drive highly reactive loads (such as an lc filter). driving an lc filter without a transformer requires that the filter be doubly terminated for best performance, that is, the filter input and output should both be resistively terminated with the appropriate val ues. the parallel combination of the two terminations will determine the load that the ad9873 will see for signals within the filter pass- band. for example, a 50 ? terminated input/output low-pass filter will look like a 25 ? load to the ad9873. the output compli ance voltage of the ad9873 is 0.5 v to +1.5 v. any signal developed at the dac output should not exceed +1.5 v, otherwise, signal distortion will result. furthermore, the signal may extend below ground as much as 0.5 v without damage or signal distortion. the ad9873 true and complement outputs can be differentially combined for common mode rejection using a broadband 1:1 transformer. using a grounded center-tap results in signals at the ad9873 dac output pins that are symmetrical about ground. as previously mentioned, by differentially combining the two signals the user can provide some degree of common mode signal rejection. a differential combiner might consist of a transformer or an operational amplifier. the object is to combine or amplify only the difference between two signals and to reject any common, usually undesirable, characteristic, such as 60 hz hum or clock feedthrough that is equally present on both individual signals. connecting the ad9873 true and complement outputs to the differential inputs of the gain programmable cable drivers ad 8321 or ad8323 provides an optimized solution for the standard com- pliant cable modem upstream channel. the cable driver s gain can be programmed through a direct 3-wire interface using the ad9873 s profile registers. 3 low-pass filter tx ad832x dac ad9873 ca 75 variable gain cable driver amplifier ca_enable ca_data ca_clk figure 15. cable amplifier connection msb lsb ca_data ca_clk ca enable 8 t mclk 8 t mclk 4 t mclk 4 t mclk 8 t mclk figure 16. cable amplifier interface timing programming/writing the ad8321/ad8323 cable driver amplifier gain control programming the gain of the ad832x-family cable driver ampli fier can be accomplished via the ad9873 cable amplifier control interface. four 8-bit registers within the ad9873 (one per pro file) store the gain value to be written to the serial 3-wire port. data transfers to the gain programmable cable driver amplifier are initiated by four conditions. each is described below: 1. power-up and hardware reset upon initial power-up and every hardware reset, the ad9873 clears the contents of the gain control registers to 0, which defines the lowest gain set- ting of the ad832x. thus, the ad9873 writes all 0s out of the 3-wire cable amplifier control interface. 2. software reset writing a one to bit 5 of address 00h initiates a software reset. on a software reset the ad9873 clears the contents of the gain control registers to 0 for the lowest gain and sets the profile select to 0. the ad9873 writes all 0s out of the 3-wire cable amplifier control interface if the gain was on a different setting (different from 0) before. 3. change in profile selection the ad9873 samples the profile[0], profile[1] input pins together with the two profile select bits and writes to the ad832x gain control regis- ters when a change in profile and gain is determined. the data written to the cable driver amplifier comes from the ad9873 gain control register associated with the current profile. 4. write to ad9873 cable driver amplifier control registers the ad9873 will write gain control data associated with the current profile to the ad832x whenever the selected ad 9873 cable driver amplifier gain setting is changed. once a new stable gain value has been detected (48 to 64 mclk cycles after initiation) data write starts with ca_enable going low. the ad9873 will always finish a write sequence to the cable driver amplifier once it is started. the logic controlling data transfers to the cable driver amplifier uses up to 200 mclk cycles and has been designed to prevent erroneous write cycles from occurring.
rev. 0 ad9873 C30C receive path (rx) adc theory of operation the ad9873 s analog-to-digital converters implement pipelined multistage architectures to achieve high sample rates while con- suming low power. each adc distributes the conversion over several smaller adc subblocks, refining the conversion with progressively higher accuracy as it passes the results from stage to stage. as a consequence of the distributed conversion, adcs require a small fraction of the 2 n comparators used in a tradi tional n-bit flash-type adc. a sample-and-hold function within each of the stages permits the first stage to operate on a new input sample while the remaining stages operate on preceding sam ples. each stage of the pipeline, excluding the last, consists of a low resolution flash adc connected to a switched capacitor dac and interstage residue amplifier (mdac). the residue amplifier amplifies the difference between the reconstructed dac output and the flash input for the next stage in the pipeline. one bit of redundancy is used in each one of the stages to facilitate digital correction of flash errors. the last stage simply consists of a flash adc. d/a a/d a/d sha correction logic d/a a/d sha gain ainp ainn ad9873 figure 17. adc architecture the analog inputs of the ad9873 incorporate a novel structure that merges the input sample and hold am plifiers (sha), and the first pipeline residue amplifiers into single, compact switched- capacitor circuits. this structure achieves considerable noise and power savings over a conventional implementation that uses separate amplifiers by eliminating one amplifier in the pipeline. by matching the sampling network of the input sha with the first stage flash adc, the adcs can sample inputs well beyond the nyquist frequency with no degradation in performance. the digital data outputs of the adcs are represented in straight binary format. they saturate to full scale or zero when the input signal exceeds the input voltage range. receive timing the ad9873 sends multiplexed data to the rx iq and if out- puts on every rising edge of mclk. rx sync frames the start of each rx iq data symbol. both 8-bit adcs transfer their data within four mclk cycles using 4-bit data packages (i msb, i lsb, q msb and q lsb). 10-bit and 12-bit adcs are com- pletely read on every second mclk cycle. rx sync is high for every second 10-bit adc data (if 8-bit adc is not in power- down mode). driving the analog inputs figure 19 illustrates the equivalent analog inputs of the ad9873, (a switched capacitor input). bringing clk to a logic high, opens switch 3 and closes switches s1 and s2. the input source is connected to a in and must charge capacitor c h during this time. bringing clk to a logic low opens s2, and then sw itch 1 opens followed by closing s3. this puts the input in the hold mode. ainp ainn 2k 2k v bias s1 s3 c p c p c h c h s2 ad9873 figure 19. differential input architecture the structure of the input sha places certain requirements on the input drive source. the combination of the pin capacitance, and the hold capacitance, c h , is typically less than 5 pf. the input source must be able to charge or discharge this capacitance to its n-bit accuracy in one-half of a clock cycle. when the sha goes into track mode, the input source must charge or discharge capacitor c h from the voltage already stored on c h to the new voltage. in the worst case, a full-scale voltage step on the input source must provide the charging current through the r on (100 ? ) of switch 1 and quickly (within 1/2 clk period) settle. this situation corresponds to driving a low input impedance. on the other hand, when the source voltage equals the value previously stored on c h , the hold capacitor requires no input curr ent and the equivalent input impedance is extremely high. adding series resistance between the output of the signal source and the a in pin reduces the drive requirements placed on the signal source. figure 20 shows this configuration. ainp ainn < 50 shunt < 50 v s figure 20. simple adc drive configuration the bandwidth of the particular application limits the size of this resistor. to maintain the performance outlined in the data sheet specifications, the resistor should be limited to 50 ? or less. for applications with signal bandwidths less than 10 mhz, the user may proportionally increase the size of the series resistor. al ter- natively, adding a shunt capacitance between the a in pins can rxi[7:4] t ht t tv mclk rx sync rx iq rxi[3:0] rxq[3:0] rxq[7:4] rxi[7:4]' rxi[3:0]' rxq[3:0]' rxq[7:4]' rxi[3:0]" rxi[7:4]" if-10 [11:2] if if-12 [11:0] if-10 [11:2]' if-12 [11:0]' if-10 [11:2]" if-12 [11:0]" if-10 [11:2]''' if-12 [11:0]''' if-10 [11:2]"" if-12 [11:0]"" figure 18. receive timing diagram
rev. 0 ad9873 C31C lower the ac load impedance. the value of this capacitance will depend on the source resistance and the required signal band- width. in systems that must use dc coupling, use an op amp to comply with the input requirements of the ad9873. op amp selection guide op amp selection for the ad9873 is highly application-dependent. in general, the performance requirements of any given application can be characterized by either time domain or frequency domain constraints. in either case, one should carefully select an op amp that preserves the performance of the adc. this task becomes challenging when one considers the ad9873 s high-performance capabilities, coupled with other system-level requirements such as power consumption and cost. the ability to select the optimal op amp may be further complicated either by lim ited power sup- ply availability and/or limited acceptable supplies for a desired op amp. newer high-performance op amps typically have input and output range limitations in accordance with their lower supply voltages. as a result, some op amps will be more appropriate in systems where ac-coupling is allowed. when dc-coupling is required, op amps headroom constraints (such as rail-to-rail op amps) or ones where larger supplies can be used, should be considered. analog devices offers differential output operational amplifiers like the ad8131 or ad8132. they can be used for differential or single-ended-to-differential signal conditioning with 8-bit performance to directly drive adc inputs. the ad8138 is a higher performance version of the ad8132. it provides 12-bit performance and allows different gain settings. please contact the factory or local sales office for updates on analog devices latest amplifier product offerings. adc differential inputs the ad9873 uses 1 v p-p input span for the 8-bit adc inputs and 2 v p-p for the 10- and 12-bit adcs. since not all applica- tions have a signal preconditioned for differential operation, there is often a need to perform a single-ended-to-differential conver- sion. in systems that do not need a dc input, an rf transformer with a center tap is the best method to generate differential in puts beyond 20 mhz for the ad9873. this provides all the benefits of operating the adc in the differential mode without con- trib uting additional noise or distortion. an rf transformer also has the added benefit of providing electrical isolation between the signal source and the adc. an improvement in thd and sfdr performance can be realized by operating the ad9873 in differential mode. the performance enhancement between the differential and single-ended mode is most considerable as the input frequency approaches and goes beyond the nyquist frequency (i.e., f in > fs/2). ainp ainn single-ended analog input r1 r1 r2 r2 ad9873 ad8131 figure 21. single-ended-to-differential input drive the ad8131 provides a convenient method of converting a single- ended signal to a differential signal. this is an i deal method for generating a direct coupled signal to the ad9873. the ad8131 will accept a signal swinging below 0 v and shift it to an externally provided common-mode voltage. the ad8131 configuration is shown in figure 21. ainp ainn ad9873 r r1 c figure 22. transformer-coupled input figure 22 shows the schematic of a suggested transformer circuit. transformers with turns ratios (n 2 /n 1 ) other than one may be selected to optimize the performance of a given application. for example, selecting a transformer with a higher impedance ratio (e.g., mini-circuits t16 6t with an impedance ratio of (z 2 /z 1 ) = 16 = (n 2 /n 1 ) 2 ) effectively steps up the signal amplitude, thus further reducing the driving requirements of the signal source. in figure 22, a resistor, r1, is added between the analog inputs to match the source impedance r as in the formula r1 4kv = (z 2 /z 1 )r. adc voltage references the ad9873 has three independent internal references for its 8-bit, 10-bit, and 12-bit adcs. both 8-bit adcs have a 1 v p-p input and share one internal reference source. the 10-bit and 12-bit ad cs, however, are designed for 2 v p-p input voltages with each of them having their own internal reference. figure 15 shows the proper connections of the reference pins reft and refb. external references may be necessary for systems that require high accuracy gain matching between adcs or improvements in tem- perature drift and noise characteristics. external references reft and rfb need to be centered at avdd/2 with offset volt ages as specified: reft-8: avddiq/2 + 0.25 v refb-8: avddiq/2 0.25 v reft-10, -12: avdd/2 + 0.5 v refb-10, -12: avdd/2 0.5 v a differential level of 0.5 v between the reference pins results in a 1 v p-p adc input level a in . a differential level of 1 v between the reference pins results in a 2 v p-p adc input level a in . internal reference sources can be powered down when exter- nal references are used (register address 02h). video input for sampling video-type waveforms, such as ntsc and pal signals, the video input channel provides black level clamping. figure 23 shows the circuit configuration for using the video channel input (pin 100). an external blocking capacitor is used with the on-chip video clamp circuit, to level-shift the input signal to a desired reference level. the clamp circuit auto mati- cally senses the most negative portion of the input signal, and adjusts the voltage across the input capacitor. this forces the black level of the input signal to be equal to the value pro grammed into the clamp level register (register address 07h). adc clamp level lpf dac video input clamp level + fs/2 clamp level 12 buffer 0.1 f 2 a offset ad9873 figure 23. video clamp circuit input
rev. 0 ad9873 C32C 5 4 3 2 7 6 9 8 1 11 10 16 15 14 13 18 17 20 19 22 21 12 24 23 26 25 28 27 30 29 32 33 34 35 36 38 39 40 41 42 43 44 45 46 47 48 49 50 31 37 76 77 78 79 74 75 72 73 70 71 80 65 66 67 68 63 64 61 62 59 60 69 57 58 55 56 53 54 51 52 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mqfp top view (pins down) video in agnd if12+ if12 agnd avdd reft12 refb12 avdd agnd if10+ if10 agnd avdd reft10 refb10 avdd agnd q in+ q in tx iq(1) tx iq(0) dvdd dgnd profile(1) profile(0) reset dvdd dgnd dgnd sclk cs sdio sdo dgnd tx dvdd tx pwr down ref io fsadj agnd tx agnd iq i in+ i in agnd iq reft8 refb8 agnd iq avdd iq drvdd ref clk drgnd dgnd sd sdelta0 sdelta1 dvdd sd ca_enable ca data ca clk dvdd osc oscin xtal dgnd osc agnd pll pll filter avdd pll dvdd pll dgnd pll avdd tx tx+ tx drgnd drvdd (msb) if(11) if(10) if(9) if(8) if(7) if(6) if(5) if(4) if(3) if(2) if(1) if(0) (msb) rx iq(3) rx iq(2) rx iq(1) rx iq(0) rx sync drgnd drvdd mlck dvdd dgnd tx sync (msb) tx iq(5) tx iq(4) tx iq(3) tx iq(2) ad9873 avdd 0.1 f 10 f 0.01 f 0.1 f 0.01 f 0.01 f 0.1 f 0.1 f 0.1 f 10 f 0.01 f 10 f 0.1 f 0.1 f 10 f 0.1 f 0.1 f 0.1 f 0.1 f10 f0.1 f 0.1 f external power supply decoupling dgnd tx gnd osc gnd agnd iq agnd v as v ds v dr 0.1 f 0.1 f 10 f 0.1 f 10 f figure 24. power supply decoupling power and grounding considerations in systems seeking to simultaneously achieve high speed and high performance, the implementation and construction of the printed circuit board design is often as important as the circuit design. proper rf techniques must be used in device selection, placem ent, routing, supply bypassing, and grounding. figure 24 illustrates proper power supply decoupling. split-ground technique can be used to isolate digital and high-speed clock generation noise from the analog front ends. the analog front end may be further split to minimize crosstalk between the transmit and receive sections. noise-sensitive video-if signals can also be separated from the more robust iq-adc signal path. one com- mon ground underneath the chip connects all ground splits and assures short distances for ground pin connections. figure 24 uses two separate power supplies. v as powers the analog and clock generation section of the chip while v ds is used for the digital signals of the chip. an extra power supply v dr is only needed in applications that require lower level digital outputs. d rvdd and d vdd pins should be connected together for normal mode. v ds (and v dr ) should not be directly connected to the power supply of noisy digital signal processing chips. it might even be considered as an analog supply. ferrite beads and 10 f decoupling capaci tors isolate power supplies between functional blocks. each supply pin is further decoupled with a 0.1 f multi- layer ceramic capacitor that is mounted as close as possible to the pin. in the high-speed pll and dac sections additional 0.01 f capacitors may be required as shown in figure 24.
rev. 0 ad9873 C33C evaluation board hardware the AD9873-EB is an evaluation board for the ad9873 analog front end converter. careful attention to layout and circuit design allow the user to easily and effectively evaluate the ad9873 in any application where high-resolution, and high-speed conversion is required. this board allows the user flexibility to operate the ad9873 in various configurations. several jumper or solder bridge settings are available. the adc inputs can be differentially driven by transformers or by an ad8138 when using connector j8 as the only input. differential to single-ended transmit output options include direct transformer coupled or filtered (75 mhz) and variable gain amplified by the ad8323. digital transmit (tx) inputs are designed to be driven from various word generators and allow for proper load termination. software the AD9873-EB software provides a graphical user interface that allows easy programming and read back of ad9873 register settings. three programming windows are available. the direct register access window allows ad9873 register write and read- back in decimal, binary or hexadecimal data format. the register map window provides a very easy, function orientated program- ming of ad9873 bits and registers. programming hints appear when the cursor is moved over an input field. registers are updated on every write button click. the advanced register access w indow allows programming of register access sequences. figure 25. evaluation board software
rev. 0 ad9873 C34C figure 26. evaluation board schematic first page, ad9873 and analog circuitry
rev. 0 ad9873 C35C 1 2 3 4 56 a b c d 6 5 4 3 2 1 d c b a title number revision size b date: 14-jul-2000 sheet of file: d:\ad9873\evalboard3\ad9873 rev a.ddb drawn by: martin kessler 3vd avddtx avddpll avddiq avdd drvdd dvdd dvddpll dvddosc dvddsd gnd + c1 10uf - 10v + c2 10uf - 10v l2 ferrite bead l3 ferrite bead + c11 10uf - 10v + c5 10uf - 10v l10 ferrite bead l1 ferrite bead l5 ferrite bead l6 ferrite bead l9 ferrite bead dvddtx l4 ferrite bead l7 ferrite bead l8 ferrite bead l12 ferrite bead l13 ferrite bead +c9 10uf - 10v +c10 10uf - 10v +c12 10uf - 10v +c13 10uf - 10v +c14 10uf - 10v +c15 10uf - 10v +c6 10uf - 10v +c7 10uf - 10v +c8 10uf - 10v +c3 10uf - 10v +c4 10uf - 10v gnd gnd gnd l11 ferrite bead + c16 10uf - 10v +5vrx c81 0.01uf c43 0.1uf c44 0.1uf c82 0.01uf c80 0.01uf c79 0.01uf c37 0.1uf c42 0.1uf c35 0.1uf c34 0.1uf c33 0.1uf c32 0.1uf c36 0.1uf c38 0.1uf c39 0.1uf c22 0.1uf c25 0.1uf c28 0.1uf c23 0.1uf c26 0.1uf c29 0.1uf c31 0.1uf c21 0.1uf c24 0.1uf c27 0.1uf c30 0.1uf c46 0.1uf c47 0.1uf c45 0.1uf c41 0.1uf c48 0.1uf +5vtx ad9873 evaluation board - power, digital a 22 c40 0.1uf +5vacon +3.3vacon 3vdriver +3.3vdcon tp1 tp-loop dvdd +c17 10uf - 10v oe1 1 i1 2 i2 3 i3 4 i4 5 i5 6 i6 7 i7 8 i8 9 o8 11 o7 12 o6 13 o5 14 o4 15 o3 16 o2 17 o1 18 oe2 19 gnd 10 vcc 20 u1 74lcx541 oe1 1 i1 2 i2 3 i3 4 i4 5 i5 6 i6 7 i7 8 i8 9 o8 11 o7 12 o6 13 o5 14 o4 15 o3 16 o2 17 o1 18 oe2 19 gnd 10 vcc 20 u2 74lcx541 oe1 1 i1 2 i2 3 i3 4 i4 5 i5 6 i6 7 i7 8 i8 9 o8 11 o7 12 o6 13 o5 14 o4 15 o3 16 o2 17 o1 18 oe2 19 gnd 10 vcc 20 u3 74lcx541 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 rp1 22 ohm res net 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 rp2 22 ohm res net 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 rp5 22 ohm res net 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 rp3 22 ohm res net 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 rp4 22 ohm res net j4 dut_control 1 2 3 4 8 7 6 5 rp6 22 ohm res net 2 4 u4 nc7sz04 1 3 2 sjp2 1 3 2 sjp1 d1 d0 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 clk sync sdout sdin csl sck 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 j7 db25 parallel printer port connector to pc (male) ca_pd ca_sleep 3vd 2 3 4 5 6 7 8 1 rp7 1k 3vd if[11..0] rxiq[3..0] rxsync mclk gnd r1 33 gnd gnd gnd gnd gnd gnd gnd gnd gnd 3vd 3vd 3vd invert clk delay clk sdo sdio cs sclk gnd r13 22 vccfifo r10 r11 gnd 1 2 3 4 5 6 7 8 j1 power conn. ad8323 decoupling gnd 2 x nc75z04 decoupling 3 x 74lcx541 deoupling digital receive 1 3 2 jp1 jumper 3 if0 if1 if2 if3 if4 if5 if6 if7 if8 if9 if10 if11 rxiq0 rxiq1 rxiq2 rxiq3 rxsync mclk 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 j2 header, rt ang, 50 pin sync clk gnd tp9 tp-loop avddtx tp4 tp-loop avddiq tp2 tp-loop drvdd tp3 tp-loop avdd tp8 tp-loop dvddpll tp5 tp-loop dvddsd tp6 tp-loop avddpll tp7 tp-loop dvddosc tp10 tp-loop dvddtx analog devices figure 27. evaluation board schematic second page, power and digital circuitry
rev. 0 ad9873 C36C figure 28. evaluation board pcb, assembly top side figure 29. evaluation board pcb, top layer
rev. 0 ad9873 C37C figure 30 evaluation board pcb, ground plane figure 31. evaluation board pcb, power plane
rev. 0 ad9873 C38C figure 32. evaluation board pcb, bottom layer figure 33. evaluation board pcb, assembly bottom side
rev. 0 ad9873 C39C outline dimensions dimensions shown in inches and (mm). 100-lead metric quad flatpack (mqfp) (s-100c) 0.555 (14.10) 0.551 (14.00) 0.547 (13.90) 81 100 1 50 31 30 51 top view (pins down) pin 1 80 0.742 (18.85) typ 0.486 (12.35) typ 0.015 (0.35) 0.009 (0.25) 0.029 (0.73) 0.023 (0.57) 0.921 (23.4) 0.906 (23.0) 0.685 (17.4) 0.669 (17.0) 0.791 (20.10) 0.787 (20.00) 0.783 (19.90) 0.134 (4.30) max seating plane 0.004 (0.10) max 0.010 (0.25) min 0.041 (1.03) 0.031 (0.78) 0.110 (2.80) 0.102 (2.60) controlling dimensions are in millimeters c01584C4.5C7/00 (rev. 0) printed in u.s.a.

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